1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to a reverse self aligned contact etch process.
2) Description of the Prior Art
The use of self aligned contact (SAC) processes has resulted in higher performing, lower cost, and increased density semiconductor devices. However, the etch to form the contact opening can cause damage to the spacers protecting the sidewalls of the structures adjacent to the contacts. Also, the tops of the structures adjacent to the contacts must withstand a significant overetch for the contact opening to be etched down to the substrate.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,661,054 (Kauffman et al.) shows a self aligned contact process. In order to completely remove the blanket deposited dielectric layer over the doped region, the top of the adjacent gate and silicon or nitride spacers must ondergo a substantial overetch which can cause reliability problems such as leakage.
U.S. Pat. No. 5,691,238 (Avanzino et al.) shows a reverse dual damascene process used to form an interconnect. Avanzino uses a timed etch of a metal layer to form a conductive via projecting up from a planer conductive layer. Avanzino does not address the self alignment and overetch problems solved by the present invention.